Business Wire

Imperas Delivers First RISC-V Simulator for New Vector and Bit Manipulation Specifications to Lead Customers

OXFORD, England--(BUSINESS WIRE)--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the delivery of its updated simulator for the RISC-V ...
Business Wire

Imperas Empowers RISC-V Community with riscvOVPsim

Imperas leading commercial simulation technology available for free with RISC-V Open Virtual Platform Simulator (riscvOVPsim™) for RISC-V software development, compliance and DV test developments RISC ...
Semiconductor Engineering

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures

A new technical paper titled “Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures” was published by researchers at National Tsing-Hua University, Politecnico ...
Design-Reuse

Trio team up to drive RISC-V ASIL-compliant automotive silicon

This collaboration equips SoC design teams with automotive-grade RISC-V IPs and the appropriate tools for early firmware and MCAL (Microcontroller Abstraction Layer) development. TASKING has been ...
Semiconductor Engineering

A Holistic View Of RISC-V Verification

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the ...
EDN

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...
Electronic Design

11 Myths About the RISC-V ISA

Many companies today are exploring free, open-source hardware and software as an alternative to closed, costly instruction set architectures (ISAs). RISC-V is a free, open, and extensible ISA that’s ...